1. Field of the Invention
This invention relates generally to the field of integrated circuit designs. More particularly, the present invention relates to gate layer filling on semiconductor substrates.
2. Description of the Related Art
In semiconductor processing, dummy fill patterns have been used in diffusion mask and metal mask to prevent dishing effects from chemical-mechanical polishing (CMP) and to minimize the effects of device-to-device variations in pattern density. For example, in conventional shallow trench isolation processes, N+ and P+ diffusion islands are isolated by oxide filled trenches. The formation of the shallow trench involves etching of the silicon trench patterns into a silicon trench and subsequently filling the trenches with a thick oxide layer. The oxide layer is then planarized by using processes such as CMP, resist etchback, or oxide etchback processes. In these cases, the polish rate or etch rate is a function of the pattern density, which is defined as the percentage of the area that is occupied by diffusion patterns.
In order to ensure a uniform removal of the oxide over an entire wafer or substrate, the pattern density should ideally remain relatively the same over all areas. To achieve the relatively uniform pattern density, the "white space" or field on the semiconductor substrate is often filled with dummy diffusion patterns. After filling the white space with the dummy fill patterns, circuit areas (e.g., dense diffusion patterns) and the field areas on the semiconductor substrate will have relatively similar pattern densities. It should be noted that the dummy fill patterns, also referred herein as fill pattern diffusion regions, are not used to form active semiconductor devices. Instead, the dummy fill patterns are used to produce a more even or consistent diffusion pattern density.
Dummy fill patterns are well known in the art and are described, for example, in U.S. Pat. No. 5,923,947, entitled "Method for Achieving Low Capacitance Diffusion Pattern Filling" and in U.S. Pat. No. 5,854,125, entitled "Dummy Fill Patterns to Improve Interconnect Planarity." The disclosures of these patents are incorporated herein by reference.
In conventional applications, dummy fill patterns are often applied to open spaces over a semiconductor substrate so that a global pattern density of about 50% is typically achieved regardless of the original circuit design density. Unfortunately, while such an arrangement works reasonably well for diffusion and metal masks, it is generally not acceptable for a gate mask due to degradation of endpoint signal and polysilicon to oxide etch rate selectivity. For example, FIG. 1A is a graph showing a relationship between optical emission intensity at 520 nm from a polysilicon etch plasma as a function of etch time. In this graph, the endpoint signal strength, which is used to detect the endpoint of a polishing wafer, is shown to exhibit substantial variance depending on the polysilicon pattern density. In particular, the endpoint of a sparsely patterned polysilicon layer 102 differs substantially from the endpoint of a densely patterned polysilicon layer 104.
On the other hand, FIG. 1B is a graph illustrating substantial variation of poly:oxide selectivity 110 as the percentage of digitization, which is the percentage of poly surface covered by a resist, varies. This variation results in lower selectivity for patterns with more resist. As shown, the poly:oxide selectivity drops off substantially as the digitization percentage increases from 0 to 50 percent.
Despite such drawbacks of the fill patterns in conventional gate masks, the dummy fill patterns are nevertheless used frequently for gate masks because they tend to reduce variations in polyline width or critical dimension (CD) such as electrical CD, effective channel length L.sub.eff, or the like. These variations generally result from device-to-device variations in global pattern density. For example, FIG. 1C shows a graph depicting the effect of varying gate pattern density on electrical critical dimension 112 and effective channel length 114 of an exemplary n-channel transistor. The range of pattern densities in this graph encompasses the range of typical design parameters used in conventional fabrication processes. As shown, the electrical critical dimension and the effective channel length L.sub.eff for the n-channel transistor are substantially dependent on the global pattern density at the gate layer. In particular, the overall variation attributable to the pattern density is shown to be about 25% for electrical critical dimension and about 10% for L.sub.eff. As can be appreciated by those skilled in the art, such significant variations are generally undesirable in semiconductor processing, especially in submicron processing.
Accurate control of the CDs and etch selectivity of polysilicon lines is generally of critical importance in the manufacturing of IC circuits as they affect the electrical characteristics of transistors. Precise control of these parameters is especially crucial for manufacturing application-specific ICs (ASICS) because ASICs typically exhibit a large variation in transistor density and layout.
Thus, what is needed is a method for defining and filling a gate layer targeted to a specified target pattern density so as to reduce variations in critical dimension while minimizing the degradation of endpoint signal and polysilicon to oxide selectivity.